Full-Time DFT Lead Position in Lausanne, Switzerland
At Kandou, we thrive on challenges and embrace innovation. As a team of passionate professionals in the semiconductor industry, we are a leading force in high-speed and energy-efficient chip-to-chip link solutions. We are committed to evolving alongside the electronics industry to meet the demands of both today’s and tomorrow’s customers. If you are eager to join a high-tech scale-up and motivated by pushing your limits while challenging the status quo, we invite you to explore this opportunity.
Key Responsibilities
- Lead DFT activities for next-generation products.
- Drive DFT architectures, methodologies, and tool flows for complex multi-million gate designs, including Analog/high bandwidth SerDes, DDR, and PCIe designs.
- Collaborate closely with the Physical Implementation team to define timing constraints in test modes, aiding successful tapeout convergence.
- Possess a strong understanding of ATE, with the ability to address probe and final test bring-up debugging issues, guiding the test engineering team towards successful Silicon bring-up and test program development.
- Define the test plan in close cooperation with teams, leading pattern development for functional and structural tests for final and wafer test programs.
- Work collaboratively with teams to implement device qualification solutions for HTOL.
- Drive lab bench silicon debugging to clarify ATE bring-up challenges.
Skills
- Excellent communication abilities with a strong team-oriented attitude.
- Experience in mentoring team members.
- Proficient debugging skills.
- Good scripting capabilities for automation development.
Qualifications
- 12+ years of DFT experience, including architecture specification, implementation, test pattern development, and simulation.
- Proven track record in delivering DFT solutions for complex designs.
- Experience with IJTAG methodologies.
- Familiarity with hierarchical MBIST insertion, hierarchical scan insertion, and scan compression methodologies.
- Expertise in ATPG pattern generation across various fault models and fault coverage analysis, achieving high coverage metrics.
- Strong debugging capabilities in simulating patterns with timing considerations.
- Experience in defining test mode constraints and analyzing timing reports.
- Proficient in using industry-standard EDA tools for DFT, timing, and simulation.
- Strong knowledge of System Verilog.
- Experience with chiplet-based designs is a plus.
Education
- Bachelor of Engineering in Electronics and Electrical Engineering, Computer Engineering, or an equivalent higher qualification.
If this position aligns with your career aspirations and you wish to be part of a growing company with an exciting future, we would love to hear from you. Apply online using the form below. Please note that only applications matching the job profile will be considered.
Together, We Kandou It!
Visit us at www.kandou.ai and on LinkedIn.